Avago-technologies LSI8751D manuály

Avago technologies LSI8751D Uživatelský manuál (314 strany)

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LSI53C875/875E

1

PCI to Ultra SCSI

1

I/O Processor

1

TECHNICAL

1

Preface iii

3

Contents

7

Contents ix

9

Contents xi

11

Contents xiii

13

80 MHz Clock 7-57

14

Chapter 1

15

General Description

15

1-2 General Description

16

1.2 Beneﬁts of Ultra SCSI

18

1.3 TolerANT

19

Technology

19

1.4 LSI53C875 Beneﬁts Summary

20

1.4.2 PCI Performance

21

1.4.3 Integration

21

1.4.4 Ease of Use

21

1.4.5 Flexibility

22

1.4.6 Reliability

23

1.4.7 Testability

23

1-10 General Description

24

Chapter 2

25

Functional Description

25

2.1.2 DMA Core

26

2.1.3 SCRIPTS Processor

26

2.1.4 Internal SCRIPTS RAM

27

2-4 Functional Description

28

2.4 External Memory Interface

30

2.5 PCI Cache Mode

32

2.5.2 3.3 V/5 V PCI Interface

33

2-10 Functional Description

34

PCI Cache Mode 2-11

35

2.5.6 Loopback Mode

36

2.5.7 Parity Options

36

Table 2.3 SCSI Parity Control

38

2.5.8 DMA FIFO

39

2-16 Functional Description

40

PCI Cache Mode 2-17

41

2-18 Functional Description

42

2.5.9 SCSI Bus Interface

43

PCI Cache Mode 2-21

45

2-22 Functional Description

46

PCI Cache Mode 2-23

47

2-24 Functional Description

48

2.5.11 Synchronous Operation

49

2-26 Functional Description

50

PCI Cache Mode 2-27

51

2.5.13 Interrupt Handling

52

PCI Cache Mode 2-29

53

2-30 Functional Description

54

PCI Cache Mode 2-31

55

2-32 Functional Description

56

PCI Cache Mode 2-33

57

2.5.14 Chained Block Moves

58

PCI Cache Mode 2-35

59

2-36 Functional Description

60

PCI Cache Mode 2-37

61

2.6 Power Management

62

2.6.2 Power State D3

63

2-40 Functional Description

64

Chapter 3

65

PCI Functional

65

Description

65

3.2 PCI Cache Mode

68

3.2.3 Alignment

69

PCI Cache Mode 3-7

71

PCI Cache Mode 3-9

73

3.3 Conﬁguration Registers

75

Register: 0x00

77

Register: 0x02

77

Register: 0x04

77

Register: 0x06

79

0b00 fast

80

0b01 medium

80

0b10 slow

80

0b11 reserved

80

Register: 0x08

81

Register: 0x09

81

Register: 0x0C

82

Register: 0x0D

82

Register: 0x0E

83

Register: 0x10

83

Register: 0x14

83

Register: 0x18

84

Register: 0x2C

84

Register: 0x2E

85

Register: 0x30

85

Register: 0x34

86

Register: 0x3C

87

Register: 0x3D

87

Register: 0x3E

88

Register: 0x3F

88

Register: 0x40

89

Register: 0x41

89

Register: 0x42

89

Register: 0x44

90

Register: 0x46

91

Register: 0x47

92

Chapter 4

93

Signal Descriptions

93

4-2 Signal Descriptions

94

4-4 Signal Descriptions

96

Ground Signals group

100

Table 4.4 System Signals

102

Table 4.7 Arbitration Signals

105

Table 4.9 SCSI SIgnals

107

4.1 MAD Bus Programming

114

Chapter 5

117

SCSI Operating

117

Registers

117

5-2 SCSI Operating Registers

118

Register: 0x00 (0x80)

119

5-4 SCSI Operating Registers

120

Register: 0x01 (0x81)

122

If the LSI53C875 is

123

5-8 SCSI Operating Registers

124

Register: 0x02 (0x82)

125

5-10 SCSI Operating Registers

126

Register: 0x03 (0x83)

128

Register: 0x04 (0x84)

130

Register: 0x05 (0x85)

131

used by the

133

Register: 0x06 (0x86)

134

Register: 0x07 (0x87)

135

Register: 0x08 (0x88)

136

Register: 0x09 (0x89)

137

Register: 0x0A (0x09)

138

Register: 0x0B (0x8B)

138

Register: 0x0C (0x8C)

139

5-24 SCSI Operating Registers

140

Register: 0x0D (0x8D)

142

Register: 0x0E (0x8E)

143

Register: 0x0F (0x8F)

145

5-30 SCSI Operating Registers

146

Register: 0x14 (0x94)

147

5-32 SCSI Operating Registers

148

• The LSI53C875 is selected

149

Register: 0x18 (0x98)

150

Register: 0x19 (0x99)

151

Register: 0x1A (0x9A)

151

5-36 SCSI Operating Registers

152

Register: 0x1B (0x9B)

153

5-38 SCSI Operating Registers

154

Register: 0x20 (0xA0)

155

Register: 0x21 (0xA1)

156

Register: 0x22 (0xA2)

158

Register: 0x23 (0xA3)

159

5-44 SCSI Operating Registers

160

Register: 0x27 (0xA7)

161

5-46 SCSI Operating Registers

162

Register: 0x38 (0xB8)

163

Register: 0x39 (0xB9)

166

Register: 0x3A (0xBA)

167

Register: 0x3B (0xBB)

167

5-52 SCSI Operating Registers

168

Register: 0x40 (0xC0)

169

5-54 SCSI Operating Registers

170

Register: 0x41 (0xC1)

171

Register: 0x42 (0xC2)

172

5-58 SCSI Operating Registers

174

Register: 0x43 (0xC3)

175

Register: 0x44 (0xC4)

176

Register: 0x45 (0xC5)

177

Register: 0x46 (0xC6)

178

Register: 0x47 (0xC7)

179

Register: 0x48 (0xC8)

180

Register: 0x49 (0xC9)

182

Register: 0x4A (0xCA)

185

Register: 0x4B (0xCB)

186

Register: 0x4C (0xCC)

186

Register: 0x4D (0xCD)

188

Register: 0x4E (0xCE)

189

5-74 SCSI Operating Registers

190

Register: 0x4F (0xCF)

191

5-76 SCSI Operating Registers

192

5-78 SCSI Operating Registers

194

SCRATCHB

195

5-80 SCSI Operating Registers

196

Chapter 6

197

Instruction Set of the

197

6.1.1 Sample Operation

199

6.2 Block Move Instructions

201

Command Not Used

202

Don’t Care Table Offset

202

Block Move Instructions 6-7

203

Block Move Instructions 6-9

205

OPC Instruction Deﬁned

206

6.3 I/O Instruction

208

I/O Instruction 6-15

211

I/O Instruction 6-17

213

Conﬁg ID Offset/period 00

214

Absolute Alternate Address

215

Command Table Offset

215

6.4 Read/Write Instructions

217

6.4.2 Second Dword

218

Read/Write Instructions 6-23

219

6.5.1 First Dword

222

MSG C/D I/O SCSI Phase

226

Command Condition Codes

227

6.6 Memory Move Instructions

229

6.6.2 Second Dword

231

6.6.3 Third Dword

231

from the Data Structure

233

6.7.1 First Dword

234

6.7.2 Second Dword

235

DCMD Register DBC Register

236

Chapter 7

237

BIG_LIT/

239

Table 7.6 Capacitance

240

Table 7.9 Output Signal—SERR/

240

DEVSEL/, STOP/, PERR/, PAR

241

GPIO3, GPIO4

241

7.3 AC Characteristics

246

Figure 7.6 Clock Waveforms

247

Table 7.16 Clock Timing

247

Figure 7.7 Reset Input

248

Table 7.17 Reset Input

248

• Target Timing

250

• Initiator Timing

250

• External Memory Timing

250

7.4.1 Target Timing

251

Data Driven by Memory)

256

(Addr Drvn by LSI53C875;

256

7.4.2 Initiator Timing

260

Figure 7.17 Back-to-Back Read

262

Figure 7.19 Burst Read

264

Figure 7.20 Burst Write

266

7.4.3 External Memory Timing

268

(Addr driven by LSI53C875;

269

Read Data

269

Middle Order

272

Low Order

275

Byte Enable

275

(Address driven by LSI53C875

277

High Order

281

Low order

282

7.6 SCSI Timing Diagrams

287

7.7 Package Drawings

294

Package Drawings 7-59

295

Appendix A

297

Register Summary

297

Appendix B

301

External Memory

301

Interface Diagram

301

Examples

301

counter bits 5-39

305

IX-2 Index

306

Index IX-3

307

IX-4 Index

308

Index IX-5

309

IX-6 Index

310

Index IX-7

311

IX-8 Index

312

Customer Feedback

313

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